The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

May. 03, 2017
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Sheng Zhang, Singapore, SG;

Wen-Bo Ding, Singapore, SG;

Zhi-Rui Sheng, Singapore, SG;

Chien-En Hsu, Singapore, SG;

Chien-Kee Pang, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1469 (2013.01); H01L 24/89 (2013.01); H01L 27/14685 (2013.01); H01L 27/14687 (2013.01); H01L 2224/8084 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10271 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/12043 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14 (2013.01);
Abstract

A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.


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