The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Aug. 21, 2017
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Sameer Pendharkar, Allen, TX (US);

Binghua Hu, Plano, TX (US);

Alexei Sadovnikov, Sunnyvale, CA (US);

Guru Mathur, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 21/8238 (2006.01); H01L 21/765 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 21/765 (2013.01); H01L 21/76229 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01); H01L 29/0615 (2013.01); H01L 29/0649 (2013.01);
Abstract

A semiconductor device adopts an isolation scheme to protect low voltage transistors from high voltage operations. The semiconductor device includes a substrate, a buried layer, a transistor well region, a first trench, and a second trench. The substrate has a top surface and a bottom surface. The buried layer is positioned within the substrate, and the transistor well region is positioned above the buried layer. The first trench extends from the top surface to penetrate the buried layer, and the first trench has a first trench depth. The second trench extending from the top surface to penetrate the buried layer. The second trench is interposed between the first trench and the transistor well region. The second trench has a second trench depth that is less than the first trench depth.


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