The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Jul. 27, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Hui Zang, Guilderland, NY (US);

Haiting Wang, Clifton Park, NY (US);

Hong Yu, Rexford, NY (US);

Laertis Economikos, Wappingers Falls, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 21/764 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76229 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/764 (2013.01);
Abstract

A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.


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