The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Nov. 13, 2018
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

Deqi Wang, San Jose, CA (US);

Anand Chandrashekar, Fremont, CA (US);

Raashina Humayun, Los Altos, CA (US);

Michal Danek, Cupertino, CA (US);

Assignee:

Lam Research Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/285 (2006.01); H01L 21/768 (2006.01); C23C 16/02 (2006.01); C23C 16/04 (2006.01); C23C 16/06 (2006.01); C23C 16/505 (2006.01); C23C 16/56 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28556 (2013.01); C23C 16/0245 (2013.01); C23C 16/04 (2013.01); C23C 16/045 (2013.01); C23C 16/06 (2013.01); C23C 16/505 (2013.01); C23C 16/56 (2013.01); H01L 21/28562 (2013.01); H01L 21/76856 (2013.01); H01L 21/76862 (2013.01); H01L 21/76876 (2013.01); H01L 21/76877 (2013.01); H01L 21/76879 (2013.01); H01L 21/76898 (2013.01); H01L 27/10891 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01);
Abstract

Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. The methods include performing multi-stage inhibition treatments including intervals between stages. One or more of plasma source power, substrate bias power, or treatment gas flow may be reduced or turned off during an interval. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.


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