The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Oct. 19, 2017
Applicant:

Utac Headquarters Pte. Ltd., Singapore, SG;

Inventors:

Antonio Bambalan Dimaano, Jr., Singapore, SG;

Roel Adeva Robles, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/683 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/4867 (2013.01); H01L 21/565 (2013.01); H01L 21/6835 (2013.01); H01L 23/3114 (2013.01); H01L 23/49822 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/83 (2013.01); H01L 24/85 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32058 (2013.01); H01L 2224/32106 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45139 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48229 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/8385 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/83385 (2013.01); H01L 2224/83801 (2013.01); H01L 2924/15311 (2013.01);
Abstract

Device and method of forming the device are disclosed. A device includes a buildup package substrate with top and bottom surfaces and a plurality of interlevel dielectric (ILD) layers with interconnect structures printed layer by layer and includes a die region and a non-die region on the top surface. A semiconductor die is disposed in the die and non-die regions of the package substrate and is electrically connected to the plurality of interconnect structures via a plurality of wire bonds. A plurality of conductive elements are disposed on the bottom surface of the package substrate and a dielectric layer encapsulates the semiconductor die, the wire bonds and the top surface of the buildup package substrate.


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