The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2020
Filed:
Jul. 14, 2016
Intel Corporation, Santa Clara, CA (US);
Sri Chaitra Chavali, Chandler, AZ (US);
Siddharth K. Alur, Chandler, AZ (US);
Amanda E. Schuckman, Scottsdale, AZ (US);
Amruthavalli Palla Alur, Chandler, AZ (US);
Islam A. Salama, Chandler, AZ (US);
Yikang Deng, Chandler, AZ (US);
Kristof Darmawikarta, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimagable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.