The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2020

Filed:

Jan. 10, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Youn Ji Min, Seoul, KR;

Seokhyun Lee, Hwaseong-si, KR;

Jongyoun Kim, Seoul, KR;

Kyoung Lim Suk, Suwon-si, KR;

SeokWon Lee, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 24/20 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 23/562 (2013.01); H01L 24/19 (2013.01); H01L 24/96 (2013.01); H01L 25/105 (2013.01); H01L 2224/214 (2013.01); H01L 2224/95001 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/35121 (2013.01);
Abstract

A method of fabricating a semiconductor package including forming a preliminary first insulating layer including a first opening, curing the preliminary first insulating layer to form a first insulating layer, forming a preliminary second insulating layer on the first insulating layer at least partially filling the first opening. The method includes forming a second opening in the preliminary second insulating layer at least partially overlapping the first opening. A sidewall of the first opening is at least partially exposed during forming the second opening. The preliminary second insulating layer is cured to form a second insulating layer. A barrier metal layer is formed along the sidewall of the first opening and along a sidewall of the second opening. A redistribution conductive pattern is formed on the barrier metal layer. A planarization process is performed to at least partially expose the second insulating layer.


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