The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2020

Filed:

Dec. 31, 2015
Applicant:

Stmicroelectronics, Inc., Coppell, TX (US);

Inventors:

John H. Zhang, Altamont, NY (US);

Chengyu Niu, Niskayuna, NY (US);

Heng Yang, Fishkill, NY (US);

Assignee:

STMICROELECTRONICS, INC., Coppell, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 21/8238 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 21/285 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823842 (2013.01); H01L 21/2855 (2013.01); H01L 21/28088 (2013.01); H01L 21/28132 (2013.01); H01L 21/82385 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823864 (2013.01); H01L 27/092 (2013.01); H01L 29/41783 (2013.01); H01L 29/42376 (2013.01); H01L 29/495 (2013.01); H01L 29/4958 (2013.01); H01L 29/66545 (2013.01); H01L 29/7845 (2013.01); H01L 29/7843 (2013.01);
Abstract

Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.


Find Patent Forward Citations

Loading…