The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2020

Filed:

Jun. 26, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Souvick Mitra, Essex Junction, VT (US);

Mickey Yu, Essex Junction, VT (US);

Alain F. Loiseau, Williston, VT (US);

You Li, South Burlington, VT (US);

Robert J. Gauthier, Jr., Williston, VT (US);

Tsung-Che Tsai, Essex Junction, VT (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 23/60 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0248 (2013.01); H01L 21/823821 (2013.01); H01L 23/60 (2013.01); H01L 27/0924 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge structures with reduced capacitance and methods of manufacture. The structure includes: a plurality of fin structures provided in at least one N+ type region and at least one P+ region; and a plurality of gate structures disposed over the plurality of fin structures and within the at least one N+ type region and one P+ region, the plurality of gate structures being separated in a lengthwise direction between the at least one N+ type region and the least one P+ region.


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