The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2020

Filed:

Mar. 30, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Leonard P. Guler, Hillsboro, OR (US);

Nick Lindert, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/308 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3085 (2013.01); H01L 21/02123 (2013.01); H01L 21/76885 (2013.01); H01L 29/66545 (2013.01);
Abstract

Methods and architectures for self-aligned build-up of patterned features. An initial patterned feature aspect ratio may be maintained or increased, for example to mitigate erosion of the feature during one or more subtractive device fabrication processes. A patterned feature height may be increased without altering an effective spacing between adjacent features that may be further relied upon, for example to further pattern an underlying material. A patterned feature may be conformally capped with a material, such as a metal or dielectric, in a self-aligned manner, for example to form a functional device layer on an initial pattern having a suitable space width-to-line height aspect ratio without the use of a masked etch to define the cap.


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