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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10529423 B1

PDFFull Text
Date of Patent:
Jan. 07, 2020

Filed:

Jun. 12, 2019

Dram device with embedded flash memory for redundancy and fabrication method thereof

Applicants:

United Microelectronics Corp., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;

Inventor:

Yukihiro Nagai, Saijo, JP;

Assignees:

UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;

Attorney:

Winston Hsu

Primary Examiner:

Mamadou L Diallo

Int. Cl.
CPC ...
G11C 14/00 (2006.01); G11C 29/00 (2006.01); H01L 27/11573 (2017.01); H01L 21/311 (2006.01); H01L 21/28 (2006.01); H01L 21/3213 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 27/108 (2006.01); H01L 29/792 (2006.01); G11C 11/401 (2006.01); H01L 29/51 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0018 (2013.01); G11C 29/789 (2013.01); G11C 29/824 (2013.01); H01L 21/28035 (2013.01); H01L 21/31111 (2013.01); H01L 21/32133 (2013.01); H01L 27/10894 (2013.01); H01L 27/11573 (2013.01); H01L 29/4925 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01); G11C 11/401 (2013.01); G11C 16/0466 (2013.01); G11C 2229/723 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10876 (2013.01); H01L 27/10885 (2013.01); H01L 29/40117 (2019.08); H01L 29/513 (2013.01); H01L 29/518 (2013.01);
Abstract

A DRAM device with embedded flash memory for redundancy is disclosed. The DRAM device includes a substrate having a DRAM array area and a peripheral area. The peripheral area includes an embedded flash forming region and a first transistor forming region. DRAM cells are disposed within the DRAM array area. Flash memory is disposed in the embedded flash forming region. The flash memory includes an ONO storage structure and a flash memory gate structure. A first transistor is disposed in the first transistor forming region.

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