The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Aug. 29, 2017
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chun-Hao Lin, Kaohsiung, TW;

Hsin-Yu Chen, Nantou County, TW;

Shou-Wei Hsieh, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/3105 (2006.01); H01L 29/06 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/31053 (2013.01); H01L 21/76224 (2013.01); H01L 29/0649 (2013.01); H01L 29/66545 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02271 (2013.01);
Abstract

A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; removing the second gate structure and part of the fin-shaped structure to forma first trench; forming a dielectric layer into the first trench; and planarizing part of the dielectric layer to form a single diffusion break (SDB) structure. Preferably, the top surfaces of the SDB structure and the first gate structure are coplanar.


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