The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Jul. 27, 2018
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, Hubei, CN;

Inventors:

Kun Zhang, Hubei, CN;

Fandong Liu, Hubei, CN;

Zhiliang Xia, Hubei, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 21/77 (2017.01); H01L 27/11568 (2017.01); H01L 27/11521 (2017.01); H01L 27/1157 (2017.01); H01L 27/11529 (2017.01); H01L 27/11524 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/77 (2013.01); H01L 27/1157 (2013.01); H01L 27/11521 (2013.01); H01L 27/11556 (2013.01); H01L 27/11568 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01);
Abstract

Embodiments of a method for forming a three-dimensional (3D) memory devices are disclosed. The method can comprise forming a device wafer including: forming a first channel hole penetrating a first alternating layer stack of a device wafer, forming an epitaxial layer on a bottom of the first channel hole, and forming a first channel layer on a sidewall of the first channel hole. The method can further comprise forming at least one connecting wafer, each connecting wafer including a second channel hole penetrating a second alternating layer stack without an epitaxial layer on a bottom of the second channel hole; and bonding the at least one connecting wafer and the device wafer, such that a second channel layer on a sidewall of the second channel hole in each connecting wafer is electrically connected with the first channel layer in the device wafer.


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