The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Oct. 15, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Gregorio Murtagian, Phoenix, AZ (US);

Saikumar Jayaraman, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/498 (2006.01); H01L 23/528 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 23/528 (2013.01); H01L 24/17 (2013.01);
Abstract

An electronic device may include a semiconductor package, that may include a package substrate. The package may include a semiconductor die. A plurality of package interconnects may include a first pillar extending from a surface of the package substrate. The electronic device may include a socket that may be configured to couple with the semiconductor package. The socket may include a plurality of socket interconnects configured to engage with the package interconnects. The plurality of socket interconnects may include a first contact, and the first contact may include an arm. The arm of the first contact may be configured to engage with the first pillar, and the arm may be configured to laterally displace when engaged with the first pillar. The engagement of the arm with the first pillar may establish an electrical communication pathway between the semiconductor package and the socket.


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