The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Jan. 18, 2018
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Kouassi Sebastien Kouassi, Singapore, SG;

Raj Verma Purakh, Singapore, SG;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/768 (2006.01); H01L 29/06 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76802 (2013.01); H01L 21/76224 (2013.01); H01L 29/0649 (2013.01);
Abstract

Semiconductor devices and methods of forming thereof by post layer transfer fabrication of device isolation structures are described. A substrate with first and second major surfaces is provided. Circuit components may be formed on the first major surface of the substrate and a back-end-of-line (BEOL) dielectric layer is formed over the first major surface of the substrate which covers the circuit components. A single layer transfer is performed to expose the second major surface of the substrate for processing. The second major surface of the semiconductor substrate is processed to thin down the wafer, followed by a wafer thickness uniformity improvement process. One or more device isolation structures are formed through the semiconductor substrate from the second major surface of the semiconductor substrate.


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