The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2019
Filed:
Oct. 13, 2017
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Ying-Hao Su, Hsinchu, TW;
Yu-Chung Su, Hsinchu, TW;
Yu-Lun Liu, Changhua County, TW;
Chi-Kang Chang, New Taipei, TW;
Chia-Chu Liu, Shin-Chu, TW;
Kuei-Shun Chen, Hsin-Chu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a plurality of fin structures disposed over a substrate having isolation features disposed therein and a plurality of gate structures disposed over the plurality of fin structures. The plurality of gate structures traverse the plurality of fin structures. The semiconductor device further includes a dielectric structure defined between the plurality of fin structures and the plurality of gate structures. The dielectric structure has an aspect ratio of about 5 to about 16. The dielectric structure includes a first dielectric layer disposed over the substrate and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer and the second dielectric layer are disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures.