The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2019
Filed:
Jul. 16, 2018
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/08 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 49/02 (2006.01); H01L 21/84 (2006.01); H01L 21/761 (2006.01); G06F 17/50 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0802 (2013.01); G06F 17/5036 (2013.01); H01L 21/761 (2013.01); H01L 21/76224 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 28/20 (2013.01); H01L 29/0646 (2013.01);
Abstract
A method for fabricating a semiconductor device includes providing a substrate, forming a first doped well within the substrate, and forming a second doped well within the substrate. The second doped well is non-contiguous with the first doped well. The method further includes depositing a dielectric layer over the substrate, and forming a first resistor element within the dielectric layer. The first resistor element is aligned with the first doped well. The method further includes forming a second resistor element within the dielectric layer. The second resistor element being aligned with the second doped well.