The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2019

Filed:

Feb. 21, 2018
Applicant:

Varian Semiconductor Equipment Associates, Inc., Gloucester, MA (US);

Inventors:

Min Gyu Sung, Essex, MA (US);

Sony Varghese, Manchester, MA (US);

Jae Young Lee, Bedford, MA (US);

Johannes Van Meer, Middleton, MA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/3115 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 21/306 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/26533 (2013.01); H01L 21/30604 (2013.01); H01L 21/31155 (2013.01); H01L 21/762 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01);
Abstract

A method for forming a semiconductor device may include providing a transistor structure. The transistor structure may include a set of semiconductor fins and a set of gate structures, disposed on the set of semiconductor fins, wherein an isolation layer is disposed between the set of semiconductor fins and between the set of gate structures. The method may include implanting ions into an exposed area of the isolation layer, wherein an altered portion of the isolation layer is formed in the exposed area, wherein an altered region of the set of semiconductor fins is formed in an exposed portion of the set of semiconductor fins. The altered portion of the isolation layer may have a first etch rate, wherein an unaltered portion of the isolation layer, not exposed to the ions, has a second etch rate, greater than the first etch rate.


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Sung, Min. (2019). Techniques for forming device having etch-resistant isolation oxide (U.S. Patent No. 10510870). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10510870

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