The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2019

Filed:

Jun. 22, 2017
Applicant:

Mitsubishi Electric Corporation, Chiyoda-ku, JP;

Inventors:

Munetaka Noguchi, Tokyo, JP;

Toshiaki Iwamatsu, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); H01L 29/165 (2013.01); H01L 29/66068 (2013.01); H01L 29/66893 (2013.01); H01L 29/78609 (2013.01); H01L 29/78612 (2013.01); H01L 29/78618 (2013.01);
Abstract

Provided is a semiconductor device includes a first semiconductor layer provided on a first main surface of the semiconductor substrate, a plurality of first semiconductor regions selectively provided at upper layer parts of the semiconductor layer, a second semiconductor region selectively provided at an upper layer part of each of the first semiconductor regions, a second semiconductor layer provided on a JFET region corresponding to the first semiconductor layer between the first semiconductor regions, and configured to cover at least a part of the JFET region, a gate insulating film covering the first semiconductor regions and the second semiconductor layer, a third semiconductor layer provided on the second semiconductor layer, a gate electrode provided on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film, a contact hole penetrating through the gate insulating film and the interlayer insulating film, at least the second semiconductor region being exposed to a bottom part thereof, a first main electrode provided on the interlayer insulating film, and configured to electrically connect to the second semiconductor region via the contact hole, and a second main electrode provided on a second main surface of the semiconductor substrate.


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