The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Apr. 30, 2015
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

National Chiao Tung University, Hsinchu, TW;

Inventors:

Steve S. Chung, Hsin-Chu, TW;

E. Ray Hsieh, Hsin-Chu, TW;

Kuan-Yu Chang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/88 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 29/73 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02428 (2013.01); H01L 29/0692 (2013.01); H01L 29/66977 (2013.01); H01L 29/7391 (2013.01); H01L 29/7851 (2013.01); H01L 29/165 (2013.01); H01L 29/49 (2013.01); H01L 29/7311 (2013.01);
Abstract

The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.


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