The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Sep. 26, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

William S. Dubel, Gilbert, AZ (US);

Josh B. Mastronarde, Sacramento, CA (US);

Melaku Teshome, Folsom, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2018.01); G06F 9/4401 (2018.01); G06F 1/3287 (2019.01); G06F 13/42 (2006.01); G06F 1/3234 (2019.01); G06F 1/32 (2019.01); G06T 1/20 (2006.01); G09G 5/00 (2006.01); G09G 5/36 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4418 (2013.01); G06F 1/32 (2013.01); G06F 1/3243 (2013.01); G06F 1/3287 (2013.01); G06F 9/4411 (2013.01); G06F 13/4286 (2013.01); G06T 1/20 (2013.01); G09G 5/001 (2013.01); G09G 5/363 (2013.01); G09G 2330/026 (2013.01); G09G 2352/00 (2013.01); G09G 2360/06 (2013.01); G09G 2360/08 (2013.01); G09G 2360/121 (2013.01);
Abstract

Embodiments are generally directed to automatic waking of power domains for graphics configuration requests. An embodiment of an apparatus an interface to receive a graphics configuration request, wherein the graphics configuration request is directed to a target graphics register in a graphics domain; registers for storage of data, the registers including one or more configuration registers that are accessible for storage of the graphics configuration request; automatic power domain determination logic to determine a power domain for the target graphics register based on shared information accessed by the automatic power domain determination logic; and wake indication logic to determine whether the power domain for the target graphics register is in a reduced power state and, upon making a reduced power state determination, to generate a wake indication for the power domain.


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