The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Aug. 08, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Eliezer Weissmann, Haifa, IL;

Rinat Rappoport, Haifa, IL;

Michael Mishaeli, Haifa, IL;

Hisham Shafi, Haifa, IL;

Oron Lenz, Haifa, IL;

Jason W. Brandt, Austin, TX (US);

Stephen A. Fischer, Gold River, CA (US);

Bret L. Toll, Hillsboro, OR (US);

Inder M. Sodhi, Folsom, CA (US);

Alon Naveh, Ramat Hasharon, IL;

Ganapati N. Srinivasa, Portland, OR (US);

Ashish V. Choubal, Austin, TX (US);

Scott D. Hahn, Portland, OR (US);

David A. Koufaty, Portland, OR (US);

Russel J. Fenger, Beaverton, OR (US);

Gaurav Khanna, Hillsboro, OR (US);

Eugene Gorbatov, Hillsboro, OR (US);

Mishali Naik, Santa Clara, CA (US);

Andrew J. Herdrich, Hillsboro, OR (US);

Abirami Prabhakaran, Hillsboro, OR (US);

Sanjeev S. Sahagirdar, Folsom, CA (US);

Paul Brett, Hillsboro, OR (US);

Paolo Narvaez, Wayland, MA (US);

Andrew D. Henroid, Portland, OR (US);

Dheeraj R. Subbareddy, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2018.01); G06F 9/50 (2006.01); G06F 9/455 (2018.01); G06F 9/4401 (2018.01);
U.S. Cl.
CPC ...
G06F 9/4401 (2013.01); G06F 9/45558 (2013.01); G06F 9/5077 (2013.01); G06F 9/5094 (2013.01); Y02D 10/22 (2018.01); Y02D 10/36 (2018.01);
Abstract

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.


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