The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Jan. 03, 2017
Applicants:

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventor:

Meng Zhao, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/225 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01); H01L 21/324 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 29/167 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/2253 (2013.01); H01L 21/26506 (2013.01); H01L 21/26513 (2013.01); H01L 21/26586 (2013.01); H01L 21/3065 (2013.01); H01L 21/30604 (2013.01); H01L 21/324 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/167 (2013.01); H01L 29/6659 (2013.01); H01L 29/66636 (2013.01);
Abstract

The present disclosure provides PMOS transistors and fabrication methods thereof. An exemplary fabrication process of a PMOS transistor includes providing a semiconductor substrate having a surface; forming a gate structure on the surface of the semiconductor substrate; forming SiGe regions in the surface of the semiconductor substrate at two sides of the gate structure by implanting Ge ions into the semiconductor substrate; forming sidewalls on side surfaces of the gate structure and portions of surfaces of the SiGe regions close to the gate structure; removing portions of the SiGe regions at two sides of the gate structure to expose portions of the semiconductor substrate; forming trenches in the semiconductor substrate by etching the exposed portions of the semiconductor substrate at the two sides of the sidewalls; and forming source/drain regions by filling the trenches with a compressive stress material.


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