The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Oct. 09, 2018
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Anis Mahmoud Jarrar, Austin, TX (US);

David Russell Tipple, Leander, TX (US);

Colin MacDonald, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 23/528 (2006.01); H01L 27/088 (2006.01); H01L 27/06 (2006.01); H01L 23/522 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66181 (2013.01); H01L 23/5223 (2013.01); H01L 23/5286 (2013.01); H01L 27/0629 (2013.01); H01L 27/0886 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 21/823821 (2013.01); H01L 2029/7858 (2013.01);
Abstract

A FinFet capacitor structure includes a first, second, third, and fourth FinFet fin, a contiguous gate layer over the fins, first and second source/drain contacts in direct physical contact with the first FinFet fin on either side of the gate layer, a first gate contact in direct physical contact with a portion of the contiguous gate layer directly over the second FinFet fin, third and fourth source/drain contacts in direct physical contact with the third FinFet fin on either side of the gate layer, and a second gate contact in direct physical contact with a portion of the contiguous gate layer directly over the fourth FinFet fin. The first, second, third, and fourth source/drain contacts are all connected to a first power supply rail, and the first and second gate contacts are all connected to a second power supply rail.


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