The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Sep. 21, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Yoshiaki Fukuzumi, Yokkaichi, JP;

Shinya Arai, Yokkaichi, JP;

Masaki Tsuji, Yokkaichi, JP;

Hideaki Aochi, Yokkaichi, JP;

Hiroyasu Tanaka, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H01L 27/11575 (2017.01); H01L 27/11565 (2017.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/11565 (2013.01); H01L 27/11575 (2013.01); H01L 29/42344 (2013.01); H01L 29/66833 (2013.01); H01L 29/7926 (2013.01);
Abstract

A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.


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