The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

May. 06, 2018
Applicants:

United Microelectronics Corp., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;

Inventors:

Pin-Hong Chen, Tainan, TW;

Yi-Wei Chen, Taichung, TW;

Chun-Chieh Chiu, Keelung, TW;

Chih-Chieh Tsai, Kaohsiung, TW;

Tzu-Chieh Chen, Pingtung County, TW;

Chih-Chien Liu, Taipei, TW;

Assignees:

UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/22 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10894 (2013.01); H01L 21/22 (2013.01); H01L 21/2855 (2013.01); H01L 21/28061 (2013.01); H01L 21/28556 (2013.01); H01L 27/10885 (2013.01);
Abstract

The present invention provides a bit line gate structure comprising a substrate, an amorphous silicon layer disposed on the substrate, a first doped region located in the amorphous silicon layer, a titanium silicon nitride (TiSiN) layer, located in the amorphous silicon layer, and a second doped region located in the TiSiN layer, the first doped region contacts the second doped region directly.


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