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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10490569 B1

PDFFull Text
Date of Patent:
Nov. 26, 2019

Filed:

Jun. 27, 2018

Three-dimensional memory device and method of making the same using concurrent formation of memory openings and contact openings

Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Mitsuteru Mushiga, Yokkaichi, JP;

Hisakazu Otoi, Yokkaichi, JP;

Kensuke Yamaguchi, Yokkaichi, JP;

James Kai, Santa Clara, CA (US);

Zhixin Cui, Yokkaichi, JP;

Murshed Chowdhury, Fremont, CA (US);

Johann Alsmeier, San Jose, CA (US);

Tong Zhang, Palo Alto, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:

The Marbury Law Group, PLLC

Primary Examiner:

Eric A Ward

Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11582 (2017.01); H01L 27/11573 (2017.01); H01L 27/1157 (2017.01); H01L 27/11565 (2017.01); H01L 27/11556 (2017.01); H01L 27/11524 (2017.01); H01L 23/522 (2006.01); H01L 27/11526 (2017.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/532 (2006.01); H01L 27/11519 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/022 (2013.01); H01L 21/76805 (2013.01); H01L 21/76832 (2013.01); H01L 23/5226 (2013.01); H01L 23/53295 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01);
Abstract

Multiple tier structures are stacked over a substrate. Each tier structure includes an alternating stack of insulating layers and sacrificial material layers and a retro-stepped dielectric material portion overlying the alternating stack. Multiple types of openings are formed concurrently during formation of each tier structure. Openings concurrently formed through each tier structure can include at least two types of openings that may be selected from through-tier memory openings, through-tier support openings, and through-tier staircase-region openings. Each through-tier opening is filled with a respective through-tier sacrificial opening fill structure. Stacks of through-tier sacrificial opening fill structures can be removed in stages to form various device components, which include memory stack structures, support pillar structures, and staircase-region contact via structures. The sacrificial material layers are replaced with electrically conductive layers, which are laterally electrically isolated from the staircase-region contact via structures by annular insulating spacers.

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