The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2019
Filed:
Feb. 26, 2018
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Chia-Han Lin, New Taipei, TW;
Chien-Fa Lee, Hsinchu, TW;
Hsu-Shui Liu, Pingjhen, TW;
Jiun-Rong Pai, Jhubei, TW;
Sheng-Hsiang Chuang, Hsin-Chu, TW;
Surendra Kumar Soni, Hsinchu, TW;
Shou-Wen Kuo, Hsinchu, TW;
Wu-An Weng, Hsinchu, TW;
Gary Tsai, Hsin-Chu, TW;
Chien-Ko Liao, Taichung, TW;
Ya Hsun Hsueh, Yunlin County, TW;
Becky Liao, Taichung, TW;
Ethan Yu, Changhua, TW;
Ming-Chi Tsai, Hsin-Chu, TW;
Kuo-Yi Liu, Chiayi, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.