The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

Jun. 29, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Uri Bear, Pardes-Hana, IL;

Gyora Benedek, Kiriat Bialik, IL;

Baruch Chaikin, Misgav, IL;

Jacob Jack Doweck, Haifa, IL;

Reuven Elbaum, Haifa, IL;

Dimitry Kloper, Haifa, IL;

Elad Peer, Yokneam Ilit, IL;

Chaim Shen-orr, Haifa, IL;

Yonatan Shlomovich, Givat-Ada, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 12/1009 (2016.01); G06F 12/1045 (2016.01);
U.S. Cl.
CPC ...
G06F 12/145 (2013.01); G06F 12/1009 (2013.01); G06F 12/1063 (2013.01); G06F 12/1483 (2013.01); G06F 12/1491 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/283 (2013.01); G06F 2212/651 (2013.01); G06F 2212/68 (2013.01); G06F 2212/684 (2013.01);
Abstract

Various systems and methods for detecting and preventing side-channel attacks, including attacks aimed at discovering the location of KASLR-randomized privileged code sections in virtual memory address space, are described. In an example, a computing system includes electronic operations for detecting unauthorized attempts to access kernel virtual memory pages via trap entry detection, with operations including: generating a trap page with a physical memory address; assigning a phantom page at an open location in the privileged portion of the virtual memory address space; generating a plurality of phantom page table entries corresponding to an otherwise-unmapped privileged virtual memory region; placing the trap page in physical memory and placing the phantom page table entry in a page table map; and detecting an access to the trap page via the phantom page table entry, to trigger a response to a potential attack.


Find Patent Forward Citations

Loading…