The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Nov. 04, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Vijay K. Nair, Mesa, AZ (US);

Adel A. Elsherbini, Chandler, AZ (US);

Lakshman Krishnamurthy, Portland, OR (US);

Johanna M. Swan, Scottsdale, AZ (US);

Alexander Essaian, Santa Clara, CA (US);

Torrey W. Frank, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2006.01); H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 25/162 (2013.01); H01L 23/48 (2013.01); H01L 23/5385 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 24/73 (2013.01); H01L 24/96 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 21/568 (2013.01); H01L 23/49816 (2013.01); H01L 23/5389 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/24146 (2013.01); H01L 2224/24155 (2013.01); H01L 2224/24195 (2013.01); H01L 2224/73209 (2013.01); H01L 2224/73267 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/15321 (2013.01); H01L 2924/15331 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/19105 (2013.01);
Abstract

Embodiments are generally directed to three-dimensional small form factor system in package architecture. An embodiment of an apparatus includes a first package having a first side and an opposite second side, the first package including a plurality of embedded electronic components and one or more embedded via bars, each via bar including a plurality of through vias; and a second package having a first side and an opposite second side, the second package including a plurality of embedded electronic components, wherein a first side of the first package and a second side of second package are coupled together by a plurality of connections, including at least a first connection connecting the second package to a first component of the first package and a second connection connecting the second package to a first via bar of the one or more via bars.


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