The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

May. 26, 2016
Applicant:

Zhuzhou Crrc Times Electric Co., Ltd., Zhuzhou, Hunan, CN;

Inventors:

Yunbin Gao, Hunan, CN;

Chengzhan Li, Hunan, CN;

Guoyou Liu, Hunan, CN;

Yudong Wu, Hunan, CN;

Jingjing Shi, Hunan, CN;

Yanli Zhao, Hunan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/15 (2006.01); H01L 29/423 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/167 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 21/04 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42368 (2013.01); H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 21/02255 (2013.01); H01L 21/049 (2013.01); H01L 29/0684 (2013.01); H01L 29/167 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01); H01L 29/7803 (2013.01);
Abstract

A silicon carbide MOSFET device is disclosed. The silicon carbide MOSFET device includes a gate oxide layer which is constituted by a first gate oxide layer and a second gate oxide layer. A thickness of the second gate oxide layer is larger than a thickness of the first gate oxide layer. Through dividing the gate oxide layer into two parts with different thicknesses, i.e., enabling the gate oxide layer to have a staircase shape, an electric field strength of the gate oxide layer can be effectively reduced, while a threshold voltage and a gate control property of the device are not affected. An on-resistance of the device can be reduced through increasing a width of a JFET region. A method for manufacturing the silicon carbide MOSFET device is further disclosed.


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