The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

Oct. 06, 2016
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Jin Qiu Liu, Singapore, SG;

Fan Zhang, Singapore, SG;

Lai Qiang Luo, Singapore, SG;

Xin Shu Cai, Singapore, SG;

Eugene Kong, Singapore, SG;

Zhiqiang Teo, Singapore, SG;

Fangxin Deng, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 27/24 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42328 (2013.01); H01L 21/28273 (2013.01); H01L 27/2436 (2013.01); H01L 29/42344 (2013.01); H01L 29/66659 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01); H01L 29/7835 (2013.01); H01L 29/456 (2013.01); H01L 29/665 (2013.01);
Abstract

Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memory cell region having a pair of non-volatile memory cells with a split gate. A split gate includes first and second gates. The first gate is an access gate and the second gate is a storage gate with a control gate over a floating gate. A common second S/D region is disposed adjacent to second gates of the first and second memory cells and first S/D regions are disposed adjacent to the first gates of the first and second memory cells. An erase gate is disposed over the common second S/D region. The erase gate is isolated by the second S/D and second gates by dielectric layers. A silicide block is disposed over the memory cell pair, covering the erase gate at least portions of the second gates of the memory cells.


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