The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

Jul. 03, 2018
Applicants:

United Microelectronics Corp., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;

Inventors:

Po-Han Wu, Pingtung County, TW;

Fu-Che Lee, Taichung, TW;

Chien-Cheng Tsai, Kaohsiung, TW;

Tzu-Tsen Liu, Kaohsiung, TW;

Wen-Chieh Lu, Taoyuan, TW;

Assignees:

UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10805 (2013.01); H01L 21/762 (2013.01); H01L 27/10885 (2013.01); H01L 27/10888 (2013.01); H01L 27/10891 (2013.01);
Abstract

A method for fabricating semiconductor device includes the steps of: forming a first bit line structure on a substrate; forming a first spacer adjacent to the first bit line structure; forming an interlayer dielectric (ILD) layer adjacent to the first spacer; removing part of the ILD layer and part of the first spacer to expose a sidewall of the first bit line structure; and forming a first storage node contact isolation structure adjacent to the first bit line structure, wherein the first storage node contact isolation structure contacts the first bit line structure and the first spacer directly.


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