The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

Apr. 24, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chien-Yao Huang, Taipei, CA;

Wun-Jie Lin, Hsinchu, TW;

Chia-Wei Hsu, New Taipei, TW;

Yu-Ti Su, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/94 (2006.01); H01L 27/02 (2006.01); H01L 27/08 (2006.01); H01L 29/861 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0928 (2013.01); H01L 27/0262 (2013.01); H01L 27/0266 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/94 (2013.01); H01L 27/0811 (2013.01); H01L 29/861 (2013.01);
Abstract

A capacitor cell is provided. A first PMOS transistor is coupled between a power supply and a first node, having a gate coupled to a second node. A first NMOS transistor coupled between a ground and the second node, having a gate coupled to the first node. A second PMOS transistor, having a drain coupled to the second node, a gate coupled to the second node, and a source coupled to the power supply or the first node. A second NMOS transistor, having a drain coupled to the first node, a gate coupled to the first node, and a source coupled to the ground or the second node.


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