The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2019
Filed:
Dec. 18, 2017
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Amit Agarwal, Hillsboro, OR (US);
Ram Krishnamurthy, Portland, OR (US);
Satish Damaraju, El Dorado Hills, CA (US);
Steven Hsu, Lake Oswego, OR (US);
Simeon Realov, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); G01R 31/3177 (2006.01); H03K 3/037 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31723 (2013.01); G01R 31/3177 (2013.01); G01R 31/31727 (2013.01); G01R 31/318541 (2013.01); H03K 3/0372 (2013.01);
Abstract
An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.