The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2019
Filed:
Jan. 03, 2018
Applicant:
Taiwan Semiconductor Manufacturing Company Ltd, Hsinchu, TW;
Inventors:
Cheng-Ta Wu, Chiayi County, TW;
Kuo-Hwa Tzeng, Taipei, TW;
Chih-Hao Wang, Hsinchu County, TW;
Yeur-Luen Tu, Taichung, TW;
Chung-Yi Yu, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 29/06 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0847 (2013.01); H01L 21/7624 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 29/0649 (2013.01);
Abstract
A silicon-on-insulator (SOI) substrate includes a semiconductor substrate and a multi-layered polycrystalline silicon structure. The multi-layered polycrystalline silicon structure is disposed over the semiconductor substrate. The multi-layered polycrystalline silicon structure includes a plurality of polycrystalline silicon layers stacked over one another, and a native oxide layer between each adjacent pair of polycrystalline silicon layers.