The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

Jan. 31, 2017
Applicants:

Sunedison Semiconductor Limited, Singapore, SG;

Igor Peidous, St. Peters, MO (US);

Inventors:

Igor Peidous, Eaton, OH (US);

Andrew M. Jones, Wildwood, MO (US);

Srikanth Kommu, St. Charles, MO (US);

Gang Wang, Grover, MO (US);

Jeffrey L. Libbert, O'Fallon, MO (US);

Assignee:

GlobalWafers Co., Ltd., Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01); H01L 21/36 (2006.01); H01L 21/30 (2006.01); H01L 21/46 (2006.01); H01L 29/04 (2006.01); H01L 31/036 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76254 (2013.01); H01L 21/0245 (2013.01); H01L 21/0262 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/28176 (2013.01);
Abstract

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.


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