The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

Jan. 27, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Yvonne Lin, Saratoga, CA (US);

Da-Wen Lin, Hsinchu, TW;

Peter Huang, Pleasant, CA (US);

Paul Rousseau, Sunnyvale, CA (US);

Sheng-Jier Yang, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 3/16 (2006.01); G05F 1/46 (2006.01); G05F 1/595 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); G05F 3/24 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
G05F 3/16 (2013.01); G05F 1/465 (2013.01); G05F 1/468 (2013.01); G05F 1/595 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/0657 (2013.01); H01L 29/785 (2013.01); G05F 3/247 (2013.01);
Abstract

Some embodiments relate to a two transistor band gap reference circuit. A first transistor includes a first source, a first drain, a first body region separating the first source from the first drain, and a first gate. The first drain and first gate are coupled to a DC supply terminal. The second transistor includes a second source, a second drain, a second body region separating the second source from the second drain, and a second gate. The second gate is coupled to the DC supply terminal, and the second drain is coupled to the first source. Body bias circuitry is configured to apply a body bias voltage to at least one of the first and second body regions. Other embodiments relate to FinFET devices.


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