The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

Dec. 22, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rajendra C. Dias, Phoenix, AZ (US);

Nachiket R. Raravikar, Gilbert, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/552 (2006.01); H01L 25/065 (2006.01); H01L 21/56 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3128 (2013.01); H01L 21/565 (2013.01); H01L 21/762 (2013.01); H01L 23/552 (2013.01); H01L 25/0657 (2013.01); H01L 21/02098 (2013.01); H01L 21/561 (2013.01); H01L 25/0655 (2013.01); H01L 2224/73204 (2013.01);
Abstract

Semiconductor packages with electromagnetic interference (EMI) shielding and a method of manufacture therefor is disclosed. The semiconductor packages may house single electronic components or may be a system in a package (SiP) implementation. The EMI shielding may be provided on top of and along the periphery of the semiconductor package. The EMI shielding on the periphery may be formed of cured conductive ink or cured conductive paste disposed on sidewalls of molding that encapsulates the electronic component(s) provided on the semiconductor package. The top portion of the EMI shielding may be a laminated metal sheet provided on a top surface of the molding. The semiconductor package may further have vertical portions of the EMI shielding with conductive ink filled trenches in the molding that may separate one or more electronic components from other electronic components of the semiconductor package.


Find Patent Forward Citations

Loading…