The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

Mar. 04, 2015
Applicant:

Shin-etsu Handotai Co., Ltd., Tokyo, JP;

Inventors:

Taishi Wakabayashi, Nagano, JP;

Kenji Meguro, Nagano, JP;

Masatake Nakano, Annaka, JP;

Shinichiro Yagi, Takasaki, JP;

Tomosuke Yoshida, Annaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/3205 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76256 (2013.01); H01L 21/0262 (2013.01); H01L 21/02164 (2013.01); H01L 21/02307 (2013.01); H01L 21/02381 (2013.01); H01L 21/02428 (2013.01); H01L 21/02488 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/30625 (2013.01); H01L 21/76254 (2013.01); H01L 27/12 (2013.01); H01L 21/02052 (2013.01); H01L 21/02238 (2013.01); H01L 21/32055 (2013.01);
Abstract

A method for manufacturing a bonded SOI wafer by bonding a bond wafer and a base wafer, each composed of a silicon single crystal, via an insulator film, including the steps of: depositing a polycrystalline silicon layer on the bonding surface side of the base wafer, polishing a surface of the polycrystalline silicon layer, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the polycrystalline silicon layer of the base wafer and the bond wafer via the insulator film, and thinning the bonded bond wafer to form an SOI layer; As a result, it is possible to provide a method for manufacturing a bonded SOI wafer which can prevent single-crystallization of polycrystalline silicon while suppressing an increase of the warpage of a base wafer even when the polycrystalline silicon layer to function as a carrier trap layer is deposited sufficiently thick.


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