The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

Mar. 15, 2018
Applicant:

Powertech Technology Inc., Hsinchu County, TW;

Inventors:

Kun-Yung Huang, Hsinchu County, TW;

Yen-Ju Chen, Hsinchu County, TW;

Assignee:

Powertech Technology Inc., Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/568 (2013.01); H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 23/3114 (2013.01); H01L 23/5226 (2013.01); H01L 24/08 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02372 (2013.01);
Abstract

A manufacturing method of a package structure is provided. The method includes the following steps. A semiconductor chip is bonded on a carrier, wherein the semiconductor chip comprises a plurality of conductive pads. An insulating material layer is formed over the carrier and encapsulating the semiconductor chip, wherein a thickness of the insulating material layer is greater than a thickness of the semiconductor chip. A first surface of the insulating material layer is patterned to form first openings that expose the conductive pads of the semiconductor chip, and second openings that penetrate through the insulating material layer. A plurality of conductive posts is formed in the first openings, wherein the plurality of conductive posts is electrically connected to the plurality of conductive pads of the semiconductor chip. A plurality of conductive vias is formed in the second opening.


Find Patent Forward Citations

Loading…