The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Sep. 27, 2017
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Masanori Tsutsumi, Yokkaichi, JP;

Naohiro Hosoda, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11575 (2017.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/76895 (2013.01); H01L 27/1157 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01);
Abstract

A three-dimensional memory device includes laterally spaced apart vertically alternating stacks of insulating strips and word line electrically conductive strips located over a substrate, memory stack structures extending through the multiple vertically alternating stacks, word line contact via structures contacting a top surface of the respective word line electrically conductive strips, field effect transistors overlying the word line contact via structures, and connector line structures which are electrically connected to respective subsets of the word line electrically conductive strips in different vertically alternating stacks through the field effect transistors.


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