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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10446676 B1

PDFFull Text
Date of Patent:
Oct. 15, 2019

Filed:

Sep. 09, 2017

Heterostructure power transistor with alsin passivation layer

Applicant:

Power Integrations, Inc., San Jose, CA (US);

Inventors:

Jamal Ramdani, Raritan, NJ (US);

Michael Murphy, Middlesex, NJ (US);

John Paul Edwards, Verona, NJ (US);

Assignee:

Power Integrations, Inc., San Jose, CA (US);

Attorney:

The Law Offices of Bradley J. Bereznak

Primary Examiner:

Yu-Hsi D Sun

Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 21/02 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01); H01L 29/201 (2006.01); H01L 29/205 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 21/0217 (2013.01); H01L 21/0254 (2013.01); H01L 21/02107 (2013.01); H01L 21/02178 (2013.01); H01L 29/201 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/42364 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/66462 (2013.01); H01L 29/42376 (2013.01); H01L 29/517 (2013.01);
Abstract

A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.

Find Patent Forward Citations

Ramdani, Jamal. (2019). Heterostructure power transistor with alsin passivation layer (U.S. Patent No. 10446676). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10446676

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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