The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Feb. 26, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Xiuyu Cai, Niskayuna, NY (US);

Ying Hao Hsieh, Clifton Park, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Caymay, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 21/8234 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6656 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823864 (2013.01); H01L 27/092 (2013.01); H01L 29/6653 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/7848 (2013.01); H01L 21/823418 (2013.01); H01L 21/823468 (2013.01); H01L 29/165 (2013.01);
Abstract

Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth ('mouse ears') on the transistor gate is prevented.


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