The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Sep. 09, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kimin Jun, Hillsboro, OR (US);

Sansaptak Dasgupta, Hillsboro, OR (US);

Alejandro X. Levander, Santa Clara, CA (US);

Patrick Morrow, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/423 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7781 (2013.01); H01L 29/2003 (2013.01); H01L 29/42356 (2013.01); H01L 29/42376 (2013.01); H01L 29/66462 (2013.01); H01L 21/76254 (2013.01); H01L 29/66545 (2013.01);
Abstract

A multi-gate high electron mobility transistor (HEMT) and its methods of formation are disclosed. The multi-gate HEMT includes a substrate and an adhesion layer on top of the substrate. A channel layer is disposed on top of the adhesion layer, and a first gate electrode is disposed on top of the channel layer. The first gate electrode has a first gate dielectric layer in between the first gate electrode and the channel layer. A second gate electrode is embedded within the substrate and beneath the channel layer. The second gate electrode has a second gate dielectric layer completely surrounding the second gate electrode. A pair of source and drain contacts are disposed on opposite sides of the first gate electrode.


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