The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Sep. 21, 2018
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Ronilo Boja, Gilroy, CA (US);

Inderjit Singh, Saratoga, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/52 (2006.01); H01L 23/488 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3114 (2013.01); H01L 21/52 (2013.01); H01L 23/488 (2013.01);
Abstract

A chip package assembly, a package substrate and methods for fabricating the same are disclosed herein. In one example, a chip package assembly includes a package substrate, an IC die and a stiffener. The package substrate includes a first dam projecting from a top surface of the package substrate. The IC die and the stiffener are mounted to the top surface of the package substrate. The stiffener includes a bottom surface that is disposed adjacent to the first dam. At least one surface mounted component is mounted to a region of the package substrate defined between the stiffener and the IC die. An adhesive coupling the stiffener to the package substrate is in contact with the first dam.


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