The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Nov. 22, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Shahab Siddiqui, Clifton Park, NY (US);

Beth Baumert, Ballston Lake, NY (US);

Abu Naser M. Zainuddin, Ballston Lake, NY (US);

Luigi Pantisano, Saratoga Spring, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); C23C 16/455 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); C23C 16/50 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823462 (2013.01); C23C 16/45525 (2013.01); C23C 16/50 (2013.01); H01L 21/0214 (2013.01); H01L 21/0223 (2013.01); H01L 21/0228 (2013.01); H01L 21/02164 (2013.01); H01L 21/02178 (2013.01); H01L 21/02181 (2013.01); H01L 21/02186 (2013.01); H01L 21/02192 (2013.01); H01L 21/02247 (2013.01); H01L 21/02252 (2013.01); H01L 21/02274 (2013.01); H01L 21/28088 (2013.01); H01L 21/28194 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 27/0886 (2013.01); H01L 29/42364 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/66545 (2013.01);
Abstract

At least one method, apparatus and system are provided for forming a hybrid oxide layer for providing for a first region of a finFET device to operate at a first voltage and a second region of the finFET to operate at a second voltage. A first set of fins are formed on an I/O device portion, and a second set of fins are formed on a core device portion of a substrate. A first and a second oxide layers are deposited on the first and second set of fins, wherein they merge to form a hybrid oxide layer. The thickness of the second oxide layer is based on a first operating voltage for the I/O device portion. The hybrid layer is removed from the core device portion such that the I/O device portion operates at the first voltage and the core device portion operates at a second voltage.


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