The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2019

Filed:

Dec. 21, 2016
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Andreas Haertl, Ottobrunn, DE;

Martin Brandt, Garching, DE;

Andre Rainer Stegner, Munich, DE;

Martin Stutzmann, Erding, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/739 (2006.01); H01L 29/861 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0626 (2013.01); H01L 29/0649 (2013.01); H01L 29/0684 (2013.01); H01L 29/401 (2013.01); H01L 29/408 (2013.01); H01L 29/7395 (2013.01); H01L 29/7811 (2013.01); H01L 29/8611 (2013.01); H01L 29/402 (2013.01); H01L 29/404 (2013.01); H01L 29/407 (2013.01); H01L 29/41758 (2013.01);
Abstract

A power semiconductor device includes a semiconductor substrate including at least one electrical structure. The at least one electrical structure has a blocking voltage of more than 20V. Further, the power semiconductor device includes an electrically insulating layer structure formed over at least a portion of a lateral surface of the semiconductor substrate. The electrically insulating layer structure embeds one or more local regions for storing charge carriers. Further, the one or more local regions includes in at least one direction a dimension of less than 200 nm.


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