The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2019

Filed:

Jan. 09, 2018
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

I-Ting Lin, Hsinchu, TW;

Yuan-Chieh Chiu, Hsinchu County, TW;

Hong-Ji Lee, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11578 (2017.01); G11C 14/00 (2006.01); G11C 16/04 (2006.01); H01L 21/28 (2006.01); H01L 27/1157 (2017.01); G11C 16/34 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11578 (2013.01); G11C 11/5671 (2013.01); G11C 14/0018 (2013.01); G11C 16/0466 (2013.01); G11C 16/3422 (2013.01); H01L 21/28282 (2013.01); H01L 27/1157 (2013.01);
Abstract

A three-dimensional non-volatile memory and a method of manufacturing the same are provided. The three-dimensional non-volatile memory includes a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed at a side of the charge storage structure and includes insulating layers, gates, a buffer layer and a barrier layer. The insulating layers and the gates are alternately stacked. The buffer layer is disposed between each of the gates and the charge storage structure and on the surfaces of the insulating layers. The barrier layer is disposed between each of the gates and the buffer layer. An end of the gate is convex with respect to an end of the barrier layer in a direction away from the channel layer.


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