The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Aug. 07, 2018
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Nhan Do, Saratoga, CA (US);

Chien-Sheng Su, Saratoga, CA (US);

Jeng-Wei Yang, Zhubei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 21/321 (2006.01); H01L 29/423 (2006.01); H01L 23/532 (2006.01); H01L 29/08 (2006.01); H01L 27/11521 (2017.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 29/49 (2006.01); H01L 21/324 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/3215 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42328 (2013.01); H01L 21/28273 (2013.01); H01L 21/31111 (2013.01); H01L 21/3212 (2013.01); H01L 21/32133 (2013.01); H01L 23/53271 (2013.01); H01L 27/11521 (2013.01); H01L 29/0847 (2013.01); H01L 29/4933 (2013.01); H01L 29/665 (2013.01); H01L 29/6656 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01); H01L 21/0274 (2013.01); H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 21/26513 (2013.01); H01L 21/324 (2013.01); H01L 21/32155 (2013.01);
Abstract

A memory device includes a semiconductor substrate having spaced apart source and drain regions, with a channel region of the substrate extending there between, a floating gate of polysilicon disposed over and insulated from a first portion of the channel region by insulation material having a first thickness, wherein the floating gate has a sloping upper surface that terminates in a sharp edge, a word line gate of polysilicon disposed over and insulated from a second portion of the channel region by insulation material having a second thickness, and an erase gate of polysilicon disposed over and insulated from the source region by insulation material having a third thickness, wherein the erase gate includes a notch that wraps around and is insulated from the sharp edge of the floating gate. The third thickness is greater than the first thickness, and the first thickness is greater than the second thickness.


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